As progress in the art of binary data processing proceeds, that data must be transmitted and processed at ever increasing rates. There have been developed in the art, both serial and parallel types of data processing systems, each with unique considerations in their individual structure, however, in both types of systems a fundamental goal has been the achievement of the transmission of higher numbers of binary bits per signal.
In serial types of systems there is a constraint in that a single signal must handle both the information signals and the clock. The solution in the art has been to use a phase locked loop, however the time that must be allotted for a phase lock related signal is characteristically very long compared to a bit time. The time difference complicates timing and frequently makes serial communication systems impractical. The phase locked loop also precludes bidirectional use of a serial channel In parallel types of systems a clock signal can be separated from the data signal but here a downside aspect exists in the timing considerations of the clock and the data.
In all systems at the present state of the art further constraints are encountered where in processing there is skewing of the shape of the data bits. Periodically, in present systems, steps for restoration of timing precision and bit reshaping must be employed.